HOME ABOUT US AWARDS SEMINAR HISTORY EXECUTIVE COMMITTEE CONTACT US
COURSES
 

Summer School in Electronics & Computers
(SUSIEC18)

- Brochure -
- Syllabus -
- Form -

---------------
 

 

 

 

 

 
 

 

VHDL- FPGA DESIGN

Duration: 10 days

Course Contents:

1. Introduction to VLSI Design

2. Need for VHDL and FPGA Design

3. Digital Design

4. Advanced Logic design

5. VHDL-Levels of Modeling

6. Data Types

7. Structural Modeling

8. Behavioral Modeling

9. Concurrent Statements

10. Functions and procedures

11. Packages

12. Finite State Machines

13. Advanced VHDL Coding

14. Introduction to FPGA's and Architectures

-------------------------------------------------------------------------------------------------------------------------------------------
Faculty: From reputed institutions IISc, LRDE, ISRO, ADA and Premier education institutions.
Days: Saturdays and Sundays
Timing: flexible
Course details & Fees: Contact Hony. Secretary at 080-2333 1133, 080-2333 7231
(including Course material in CD & coffee)
Duration: Three hours /day (4days to 10 days)
Venue: IETE Bangalore Centre
-------------------------------------------------------------------------------------------------------------------------------------------

 

--------------
AGM-2018 Notice

Minutes of
AGM-2017

Balance Sheet
2017 - 2018

Annual Report
2017 - 2018

--------------

© IETE Bangalore Centre 2010. All rights reserved