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SUMMER CLASSES

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SUSIE - 2017
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SUSIE FORM
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BASIC COMPUTER COURSE-2017

FOUNDATION COURSE IN MATHEMATICS

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Weekend Course on Advanced FPGA Design with Lab Session

Topic:

1) Introduction to FPGA Design and FPGA design Flow
     a. PAL,CPLD and FPGA basics
     b. FPGA Design Flow

2) FPGA Architecture
     a. Internal Architecture of FPGA and CPLD
     b. Logic implementation

3) HDL Basic
     a. Introduction to VHDL/VERILOG
     b. Design methodology using VHDL/VERILOG

4) FPGA Simulation and Synthesis Tool Flow
     a. Modelsim/Aldec simulation
     b. Design Synthesis using Synplify PRO

5) FPGA Implementation Design Flow
     a. Design constraining and pin locking
     b. Static Timing Analysis

6) Timing Simulation and Programming
     a. Timing Simulation using Modelsim/Aldec
     b. Programming using JTAG

7) System Level testing and debugging
     a. Debugging techniques
     b. Identification of the issues/resolving

8) Misc Topics
     a. FPGA Device selection
     b. Other Q&A

Note: 1) Labs will be conducted for the above sessions with the Hardware

 

 

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AGM-2017 Notice

Minutes of
AGM-16

Balance Sheet

Annual Report
2016 - 2017

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